View PI6C49018ZDIE_8618274.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1 pi6c49018 block diagram description the pi6c49018 is a clock generator device intended for pci- express/networking applications. the device includes four 100 mhz differential outputs for pci-express with low power hcsl structure, one cmos 125 mhz output, and one cmos 66.6 6 mhz, and one cmos 80 mhz output with spread spectrum. using a serially programmable smbus interface, the pi6c49018 incorporates spread spectrum modulation on the four 100 mhz pci-express outputs with -0.5% down spread and the 80 mhz output with selectable down spread. low power networking clock generator features ?? 25 mhz crystal or clock input ?? four diferential 100 mhz pci-express clock outputs C low power hcsl ?? spread spectrum capability on all 100 mhz pci-e clock outputs with -0.5% down spread ?? one single-ended 66.66 mhz output ?? one single-ended 125 mhz output for gigabit ethernet at 2.5v ?? one single-ended 80 mhz output with selectable down spread ?? 40-pin tqfn package ?? operating voltage 3.3 v 5% ?? industrial temperature (-40 to +85c) www.pericom.com pi6c49018 rev . a 12/10/2014 14-0209
2 pin configuration pin# pin name pin ty pe pin description 1 vdd power 3.3v supply pin 2 gnd power ground 3 vdd power 3.3v supply pin 4 pcie3n output diferential 100 mhz pci express clock output 5 pcie3 output diferential 100 mhz pci express clock output 6 gnd power ground 7 vdd power 3.3v supply pin 8 sclk input smbus clock input 9 sdata i/o smbus data input 10 gnd power ground 11 80m output 80 mhz lvcmos output. tri-state with weak pull- down when disabled 12 vdd power 3.3v supply pin 13 vdd power 3.3v supply pin 14 gndx power ground pin description 1 gnd 40 -p in qfn vdd gnd gnd vdd gnd vdd gnd pcie0 gnd vdd vdd gndx pd_reset 11 21 31 pcie3 vdd pcie3n vdd sclk sdata gnd 80m x1 x2 vddx vddo 125m 6 6.66m 60m vdd gnd vdd pcie0n pcie1 pcie1n vdd cdd pcie2n pcie2 vdd www.pericom.com pi6c49018 rev . a 12/10/2014 pi6c49018 low power networking clock generator 14-0209
3 pin description pin# pin name pin ty pe pin description 15 pd_reset input global reset input powers down plls plus tri-states outputs and sets the i2c tables to their default state when pulled low. controlled by external por 16 x1 xi crystal input. connect to 25 mhz fundamental mode crystal or clock 17 x2 xo crystal output. connect to 25 mhz fundamental mode crystal. float for clock input 18 vddx power 3.3v supply pin for oscillator 19 vddo power 125 mhz output supply voltage. connect to +2.5 v 20 125m output 125 mhz, +2.5 v lvcmos output. tri-stated with a weak pull-down when disabled 21 gnd power ground 22 vdd power 3.3v supply pin 23 66. 66 m output 66. 66 mhz lvcmos output. tri-stated with a weak pull-down when disabled 24 gnd power ground 25 vdd power 3.3v supply pin 26 gnd power ground 27 60m output 60 mhz lvcmos output. tri-state with weak pull- down when disabled 28 vdd power 3.3v supply pin 29 gnd power ground 30 vdd power 3.3v supply pin 31 pcie0n output diferential 100 mhz pci express clock output 32 pcie0 output diferential 100 mhz pci express clock output 33 pcie1 output diferential 100 mhz pci express clock output 34 pcie1n output diferential 100 mhz pci express clock output 35 vdd power 3.3v supply pin 36 gnd power ground 37 vdd power 3.3v supply pin 38 cdd input input pin for of chip bypass capacitor. connect to 0.01 f capacitor 39 pcie2n output diferential 100 mhz pci express clock output 40 pcie2 output diferential 100 mhz pci express clock output www.pericom.com pi6c49018 rev . a 12/10/2014 pi6c49018 low power networking clock generator 14-0209
4 selection table 1 C 80m spread spectrum ss1 ss0 ssc 0 0 -1% 0 1 off 1 0 -0.5% 1 1 -0.75% note: refer to byte0 control register . default setting is ss1:ss0 = 01 www.pericom.com pi6c49018 rev . a 12/10/2014 pi6c49018 low power networking clock generator 14-0209
5 serial data interface (smbus) this part is a slave only smbus device that supports indexed block read and indexed block write protocol using a single 7-bit ad - dress and read/write bit as shown below. address assignment a6 a5 a4 a3 a2 a1 a0 w/r 1 1 0 1 0 0 1 0/1 how to write 1 bit 8 bits 1 8 bits 1 8 bits 1 8 bits 1 8 bits 1 1 bit start bit d2h ack register ofset ack byte count = n ack data byte 0 ack data byte n - 1 ack stop bit note: 1. register of fset for indicating the starting register for indexed block write and indexed block read. byte count in write mode cannot be 0. byte 0: spread spectrum control register bit description type power up condition output(s) afected notes 7 spread select for 100 mhz push-pull pci-express clocks rw 0 all 100mhz pci- express outputs 0=spread of 1 = -0.5% down spread 6 enables hardware or sofware control of oe bits (see byte 0-bit 6 and bit 5 functionality table) rw 0 pd_reset , bit 5 0 = hardware cntl 1 = sofware ctrl 5 sofware pd_reset bit. enables or disables all out- puts. (see byte 0-bit 6 and bit 5 functionality table) rw 1 all outputs 0 = disabled 1 = enabled 4 spread select for 80mhz ss1 rw 0 80m see table 1 on page4 3 spread select for 80mhz ss0 rw 1 2 oe for 66.66 mhz output rw 1 66.66m 0 = disabled 1 = enabled 1 reserved r - - - 0 oe for single-ended 125mhz rw 1 single-ended 125mhz 0 = disabled 1 = enabled how to read (m: abbreviation for master or controller; s: abbreviation for slave/clock) 1 bit 8 bits 1 bit 8 bits 1 bit 1 bit 8 bits 1 bit 8 bits 1 bit 8 bits 1 bit 8 bits 1 bit 1 bit m: start bit m: send "d2h" s: sends ack m: send starting databyte location: n s: sends ack m: start bit m: send "d3h" s: sends ack s: sends # of data bytes that will be sent: x m: sends ack s: sends start - ing data byte n m: sends ack s: sends data byte n+x-1 m: not ac - knowl - edge m: stop bit www.pericom.com pi6c49018 rev . a 12/10/2014 pi6c49018 low power networking clock generator 14-0209
6 byte 1: control register bit description type power up condi- tion output(s) afected notes 7 oe for 80 mhz output rw 1 80mhz 0 = disabled 1 = enabled 6 to 0 reserved r - - - bit description type power up condi- tion output(s) afected notes 7 to 0 reserved r - - - byte 2: control register byte 3: spread spectrum control register bit description type power up condition output(s) afected notes 7 oe for 60mhz output rw 0 60m 1 = enabled 0 = disabled 6 reserved r - - - 5 oe for 100mhz hcsl pci-express output pcie3 rw 0 100mhz hcsl pci-express output pcie3 1 = enabled 0 = disabled 4 oe for 100mhz hcsl pci-express output pcie2 rw 1 100mhz hcsl pci-express output pcie2 1 = enabled 0 = disabled 3 reserved r - - - 2 oe for 100mhz hcsl pci-express output pcie1 rw 1 100mhz hcsl pci-express output pcie1 1 = enabled 0 = disabled 1 oe for 100mhz hcsl pci-express output pcie0 rw 1 100mhz hcsl pci-express output pcie0 1 = enabled 0 = disabled 0 reserved r - - - byte 0: bit 6 and bit 5 functionality bit 6 bit 5 description 0 x ( pd_reset = "h" will enable all outputs; smbus cannot control each output.) 1 0 disables all outputs and tri-states the outputs, pd_reset hw pin/signal = do not care 1 1 enable outputs according to the smbus default values; smbus can control each output. pd_reset hw pin/signal = do not care www.pericom.com pi6c49018 rev . a 12/10/2014 pi6c49018 low power networking clock generator 14-0209
7 byte 5: control register bit description type power up condition output(s) afected notes 7 revision id bit 3 r 0 - - 6 revision id bit 2 r 0 - - 5 revision id bit 1 r 0 - - 4 revision id bit 0 r 0 - - 3 vendor id bit 3 r 0 - - 2 vendor id bit 2 r 0 - - 1 vendor id bit 1 r 0 - - 0 vendor id bit 0 r 0 - - bit description type power up condi- tion output(s) afected notes 7 to 0 reserved r - - - byte 6: control register bit description type power up condi- tion output(s) afected notes 7 to 0 reserved r - - - byte 4: control register www.pericom.com pi6c49018 rev . a 12/10/2014 pi6c49018 low power networking clock generator 14-0209
8 maximum supply voltage, v dd .............................................................. 7v all inputs and outputs ................................................ C0.5v to v dd +0.5v ambient operating temperature ....................................... C40c to +85c storage temperature ........................................................ C65c to +150c junction temperature ........................................................................ 125c peak soldering temperature ..............................................................260c esd protection (hbm).................................................................... 2000v note: stresses above the ratings listed below can cause permanent damage to the pi6c49018. these ratings, which are standard values for pericom commercially rated parts, are stress ratings only. functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifcations is not implied. exposure to absolute maximum rating conditions for extended periods can affect product reliability. electrical parameters are guaranteed only over the recommended operating temperature range. maximum ratings (above which useful life may be impaired. for user guidelines, not tested.) dc electrical characteristics unless otherwise specifed, v dd =3.3v10%, v ddo =2.5v,ambient temperature C40c to +85c parameter symbol conditions min typ max units operating supply voltage v dd 3.135 3.3 3.465 v output supply voltage v ddo 2.25 2.5 3.6 input high voltage v ih x1/sclk, sdata 2 v dd input low voltage v il x1/sclk, sdata C0.3 0.8 operating supply current i dd no load, all supply pins, pd_reset = 1 50 75 105 ma idd at output disable condition i ddpd pd_reset = 0 1 short circuit current i os all single-ended clocks 35 internal pull-up/pull- down resistor r pu /r pd pd_reset 240 k? all single-ended clocks 110 output capacitance z o 30 pf input capacitance c in all input pins 6 ? recommended operation conditions parameters min. typ. max. units ambient operating temperature -40 +85 c power supply voltage (measured in respect to gnd) +3.135 3.3 +3.465 v output supply voltage, v ddo +2.25 +3.6 v minimum pulse width of pd_reset input 100 ns www.pericom.com pi6c49018 rev . a 12/10/2014 pi6c49018 low power networking clock generator 14-0209
9 electrical characteristics - single-ended unless otherwise specifed, v dd =3.3v10%, v ddo =2.5v, ambient temperature C40c to +85c parameter symbol conditions min typ max units input clock frequency f in 25 mhz output frequency error 0 ppm output rise time t or at v dd /2 0.5 1 ns 0.7 v to 1.7v 125 mhz 0.4 output fall time t of at v dd /2 0.5 1 output clock duty cycle measured at v dd /2, 125mhz 47 50 53 % measured at v dd /2, all other outputs 45 50 55 output high voltage v oh i oh = -4ma vdd-0.4 v output high voltage v oh i oh = -8ma 2.4 v output low voltage v ol i ol = 4ma 0.4 v output low voltage v ol i ol = 8ma 0.4 v peak-to-peak jitter 66.66mhz clock output 150 ps 125mhz clock output 100 60mhz clock output 200 cycle-to-cycle jitter 125mhz clock output 100 60m/66.66m/80mhz clock output 250 phase noise 60m/66.66 mhz, 500 khz ofset -100 db modulation rate 80mhz clock output 32 60 khz clock stabilization time from power up pd_reset goes high to 1% of fnal frequency 3 10 ms note 1: cl = 15 pf note 2: cycle-to-cycle jitter is measured at 25c. note 3: spread off. www.pericom.com pi6c49018 rev . a 12/10/2014 pi6c49018 low power networking clock generator 14-0209
10 electrical characteristics - 100mhz differential hcsl outputs unless otherwise specifed, v dd =3.3v 10%, ambient temperature C40c to +85c parameter symbol conditions min ty p max units output frequency 100 mhz cycle-to-cycle jitter t cc/jitter 150 ps peak-to-peak phase jitter t j? pcie gen1 flter function 86 spread range -0.5 0 % spread rate 32 0 khz duty cycle t dc 45 50 55 % clock stabilization from power up 3.5 ms rising edge rate note3, 4 0.6 4.0 v/ns falling edge rate note3, 4 0.6 4.0 v/ns rise-fall matching note3, 11 20% output skew t oskew v t = 50%(measurement thresh- old), intra-pair skew 50 ps v t = 50%(measurement thresh- old), inter-pair skew 200 ps clock source dc impedance(zo) z c-dc 17 ? high-level output voltage v oh note2 (rs = 33ohm) 0.65 0.71 0.85 v low-level output voltage v ol -0.20 0 0.05 v absolute crossing point voltage v cross note2, 5, 6 0.25 0.55 v variation of v cross over all rising clock edges v cross delta note2, 5, 8 140 mv average clock period accuracy t period avg note3, 9, 10 -300 2800 ppm absolute period (including jitter and spread spectrum) t period abs note3, 7 9.847 10.203 ns note:1.measured at the end of an 8-inch trace with a 5pf load. 2.measurement taken from a single-ended waveform. 3.measurement taken from a differential waveform. 4.measured from -150 mv to +150 mv on the differential waveform. the signal is monotonic through the measurement region for rise and fall time. the 300 mv measurement window is centered on the differential zero crossing. 5.measured at crossing point where the instantaneous voltage value of the rising edge of 100m+ equals the falling edge 100m-. 6.refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. refers to all crossing points for this measurement. 7.defnes as the absolute minimum or maximum period. this includes cycle-to-cycle jitter, relative ppm tolerance, and spread spectrum modulation. 8.defned as the total variation of all crossing voltages of rising 100m+ and falling 100m-. 9.refer to section 4.3.2.1 of the pci express base specifcation, revision 1.1 for information regarding ppm considerations. 10.ppm refers to parts per million and is a dc absolute period accuracy specifcation. 1 ppm is 1/1,000,000th of 100 mhz exactly or100 hz. for 300 ppm there is an error budget of 100hz/ppm * 300 ppm = 30 khz. the period is measured with a frequency counter with measurement window set at 100 ms or greater. with spread spectrum turned off the error is less than 300 ppm. with spread spectrum turned on there is an additional +2500 ppm nominal shift in maximum period resulting from the -0.5% down spread. 11.matching applies to rising edge rate for pcie and falling edge rate for pcien. it is measured using a 75 mv window centered on the median cross point where www.pericom.com pi6c49018 rev . a 12/10/2014 pi6c49018 low power networking clock generator 14-0209
11 c1 27pf crystal?(c l? =?18pf) c2 27pf xtal_in xtal_out saronix-ecera fl2500047 application notes crystal circuit connection te following diagram shows pi6c49018 crystal circuit connection with a parallel crystal. for the cl=18pf crystal, it is suggested to use c1= 27pf, c2= 27pf. c1 and c2 can be adjusted to fne tune to the target ppm of crystal oscillator according to diferent board layouts. crystal oscillator circuit recommended crystal specification pericom recommends: a f2500081 smd 5x324p 25m cl18pf -30ppm http:wwwpericomcompdfdatasheetsseffpdf b fl250004 smd 32x254p 25m cl18pf -20ppm http:wwwpericomcompdfdatasheetsseflpdf www.pericom.com pi6c49018 rev . a 12/10/2014 pi6c49018 low power networking clock generator 14-0209
12 confguration test load board termination for hcsl outputs rs 33? 5% rs 33? 5% 2pf 5% 2pf 5% clock# clock tla tlb pi6c49018 )ljxuh&rq?jxudwlrq7hvw/rdg%rdug7huplqdwlrq www.pericom.com pi6c49018 rev . a 12/10/2014 pi6c49018 low power networking clock generator 14-0209
13 ordering information (1-3) ordering code package code package description PI6C49018ZDIE zd 40-contact, thin fine pitch quad flat no-lead (tqfn) notes: 1. thermal characteristics can be found on the company web site at www.pericom.com/packaging/ 2. e = pb-free and green 3. adding an x suffx = tape/reel pericom semiconductor corporation ? 1-800-435-2336 ? www .pericom.com note: ? for latest package info, please check: http://www .pericom.com/products/packaging/mechanicals.php all trademarks are property of their respective owners. ackaging echanical: 0 n www.pericom.com pi6c49018 rev . a 12/10/2014 pi6c49018 low power networking clock generator 14-0209

▲Up To Search▲

Price & Availability of PI6C49018ZDIE

	To Download PI6C49018ZDIE Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .